1. Field of the Invention
This invention relates to a semiconductor device such as a memory having MIS transistors, for example, and more particularly to a power supply voltage lowering circuit.
2. Description of the Related Art
For example, the gate oxide film used in a semiconductor device (which is hereinafter referred to as an LSI) such as a memory device having MIS transistors is made thinner as the element is more miniaturized. External power supply voltage (which is hereinafter referred to as VEXT) applied to this type of LSI is not always changed according to miniaturization of the element. Therefore, high voltage of VEXT determined according to the environment of the user using the LSI is applied to the LSI in some cases. If the high voltage of VEXT is applied to a transistor having a thin gate oxide film in the LSI, the gate oxide film will be destroyed in some cases.
In order to prevent the above problem, a countermeasure for arranging a power supply voltage lowering circuit (which is hereinafter simply referred to as a voltage lowering circuit) in the LSI and lowering VEXT by use of the voltage lowering circuit to generate internal power supply voltage (which is hereinafter referred to as VINT) is taken. Thus, by generating VINT lower than VEXT, the transistor having a thin gate oxide film can be prevented from being destroyed. When VEXT becomes equal to or higher than constant voltage, the voltage of VINT is set to voltage which does not depend on a variation in the voltage of VEXT and a temperature variation and the voltage of VINT becomes equal to a constant value.
As the technique for generating internal power supply voltage based on the external power supply voltage by use of the voltage lowering circuit, for example, a circuit which is turned ON in response to a control signal in a low power consumption mode (deep power down mode) to generate internal power supply voltage lower than the external power supply voltage by threshold voltage VTHN of an NMOS transistor is developed (Jpn. Pat. Appln. KOKAI Publication No. 2002-373490).
Further, a circuit in which a PMOS transistor is turned ON in response to a power-ON reset signal generated at the turn-ON time of the power supply and the external power supply voltage VEXT is forcedly set to the internal power supply voltage VINT in a semiconductor device having a voltage generating circuit which generates the internal power supply voltage based on the external power supply voltage is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 2001-210076).
The conventional voltage lowering circuit includes a reference voltage generating circuit using a band gap reference circuit which generates reference voltage VREF and an internal voltage generating circuit which receives the reference voltage VREF from the voltage generating circuit and generates VINT.
For example, when no access is made to the LSI for a long period of time, the LSI is set in a standby mode in order to suppress the power consumption. When the LSI is set into the standby mode, VEXT is lowered to approximately 1V in some cases in order to suppress a standby current of the LSI. In this case, a voltage of only 0.7V is output as VINT generated from the conventional voltage lowering circuit. Since VINT is also used as the power supply voltage of the memory cell, a voltage of 0.7V is applied to the power supply of the memory cell. For example, the voltage is substantially equal to the threshold voltage VTHN of an N-channel MOS transistor (which is hereinafter referred to as an NMOS transistor) or the threshold voltage |VTHP| of a P-channel MOS transistor (which is hereinafter referred to as a PMOS transistor) which configures a memory cell of a static RAM. Therefore, the data latch ability of the memory cell is weakened. That is, when the threshold voltage VTHN of the NMOS transistor or the threshold voltage |VTHP| of the PMOS transistor which configures the memory cell becomes higher than 0.7V, there occurs a possibility that the NMOS transistor or the PMOS transistor is set into the OFF state and data stored in the memory cell will be lost.
Further, the semiconductor device is required to be miniaturized. Therefore, it is not preferable to increase the circuit scale of the voltage lowering circuit. In order to generate required internal power supply voltage, it is desirable to suppress the number of exclusive control signals and the number of circuits which generate the control signals to the smallest possible value. Therefore, it is desired to develop a semiconductor device which can suppress the internal power supply voltage from becoming lower than the external power supply voltage without using the exclusive control signal in a state such as a standby mode in which the external power supply voltage is set low and enhance the performance of the semiconductor device in the state in which the external power supply voltage is set low.